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L6382D
Power management unit for microcontrolled ballast
Features

Integrated high-voltage start-up 4 drivers for PFC, half-bridge & pre-heating MOSFETs 3.3V microcontroller compatible Fully integrate power management for all operating modes Internal two point VCC regulator Over-current protection with digital output signal Cross-conduction protection (interlocking) Under voltage lock-out Integrated bootstrap diode
SO-20
Description
The L6382D is suitable for microcontrolled electronic ballasts embedding a PFC stage and a half-bridge stage. The L6382D includes 4 MOSFET driving stages (for the PFC, for the half bridge, for the preheating MOSFET) plus a power management unit (PMU) featuring also a reference able to supply the microcontroller in any condition. Besides increasing the application efficiency, the L6382D reduces the bill of materials because different tasks (regarding drivers and power management) are performed by a single IC, which improves the application reliability.
Applications
Dimmable / non-dimmable ballast
Figure 1.
Block diagram
March 2007
Rev 6
1/22
www.st.com 22
Contents
L6382D
Contents
1 2 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 5 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1.1 6.1.2 6.1.3 6.1.4 START-UP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SAVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 OPERATING Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 7.2 7.3 7.4 Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3V reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Internal logic, over current protection (OCP) and interlocking function . . 17
8 9 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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L6382D
Device description
1
Device description
Designed in High-voltage BCD Off-line technology, the L6382D is a PFC and ballast controller provided with 4 inputs pin and a high voltage start-up generator conceived for applications managed by a microcontroller providing the maximum flexibility. It allows the designer to use the same ballast circuit for different lamp wattage/type by simply changing the C software. The digital input pins - able to receive signals up to 400KHz - are connected to level shifters that provide the control signals to their relevant drivers; in particular the L6382D embeds one driver for the PFC pre-regulator stage, two drivers for the ballast half-bridge stage (High Voltage, including also the bootstrap function) and the last one to provide supplementary features like preheating of filaments supplied through isolated windings in dimmable applications. A precise reference voltage (+3.3V 1%) able to provide up to 30mA is available to supply the C: this current is obtained thanks to the on-chip high voltage start-up generator that, moreover, keeps the consumption before start-up below 150A. The chip has been designed with advanced power management logic to minimize power losses and increase the application reliability. In the half-bridge section, a patented integrated bootstrap section replaces the external bootstrap diode. The L6382D integrates also a function that regulates the IC supply voltage (without the need of any external charge pump) and optimizes the current consumption. Figure 2. Typical system block diagram
3/22
Pin settings
L6382D
2
2.1
Pin settings
Pin connection
Figure 3. Pin connection (top view)
PFI LSI HSI HEI PFG N.C. TPR GND LSG VCC
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VREF CSI CSO HEG N.C. HVSU N.C. OUT HSG BOOT
2.2
Pin description
Table 1. Pin description
Name 1 2 3 4 Pin N PFI LSI HSI HEI Description Digital input signal to control the PFC gate driver. This pin has to be connected to a TTL compatible signal. Digital input signal to control the half-bridge low side driver. This pin has to be connected to a TTL compatible signal. Digital input signal to control the half-bridge high side driver. This pin has to be connected to a TTL compatible signal. Digital input signal to control the HEG output. This pin has to be connected to a TTL compatible signal. PFC Driver Output. This pin is intended to be connected to the PFC power MOSFET gate. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 10K resistor toward ground avoids spurious and undesired MOSFET turn-on. The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 250mA sink. Not connected Input for two point regulator; by coupling the pin with a capacitor to a switching circuit, it is possible to implement a charge circuit for the Vcc. Chip ground. Current return for both the low-side gate-drive currents and the bias current of the IC. All of the ground connections of the bias components should be tied to a trace going to this pin and kept separate from any pulsed current return.
5
PFG
6 7
N.C. TPR
8
GND
4/22
L6382D Table 1. Pin description
Name Pin N Description
Pin settings
9
LSG
Low Side Driver Output. This pin must be connected to the gate of the halfbridge low side power MOSFET. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 20K resistor toward ground avoids spurious and undesired MOSFET turn-on. The totem pole output stage is able to drive power with a peak current of 120mA source and 120mA sink. Supply Voltage for the signal part of the IC and for the drivers. High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 13 (OUT) is fed by an internal synchronous bootstrap diode driven in phase with the low-side gate-drive. This patented structure normally replaces the external diode. High Side Driver Output. This pin must be connected to the gate of the half bridge high side power MOSFET . A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 20K resistor toward OUT pin avoids spurious and undesired MOSFET turn-on The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 120mA sink. High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground. Not connected High-voltage start-up. The current flowing into this pin charges the capacitor connected between pin Vcc and GND to start up the IC. Whilst the chip is in save mode, the generator is cycled on-off between turn-on and save mode voltages. When the chip works in operating mode the generator is shut down and it is re-enabled when the Vcc voltage falls below the UVLO threshold. According to the required VREF pin current, this pin can be connected to the rectified mains voltage either directly or through a resistor. High-voltage spacer. The pin is not connected internally to isolate the highvoltage pin and comply with safety regulations (creepage distance) on the PCB. Output for the HEI block; this driver can be used to drive the MOS employed in isolated filaments preheating. An internal 20K resistor toward ground avoids spurious and undesired MOSFET turn-on. Output of current sense comparator, compatible with TTL logic signal; during operating mode, the pin is forced low whereas whenever the OC comparator is triggered (CSI> 0.5V typ.) the pin latches high. Input of current sense comparator, it is enabled only during operating mode; when the pin voltage exceeds the internal threshold, the CSO pin is forced high and the half bridge drivers are disabled. It exits from this condition by either cycling the Vcc below the UVLO or with LGI=HGI=low simultaneously. Voltage reference. During normal mode an internal generator provides an accurate voltage reference that can be used to supply up to 30mA (during operating mode) to an external circuit. A small film capacitor (0.22F min.), connected between this pin and GND is recommended to ensure the stability of the generator and to prevent noise from affecting the reference.
10
Vcc
11
BOOT
12
HSG
13 14
OUT N.C.
15
HVSU
16
N.C.
17
HEG
18
CSO
19
CSI
20
VREF
5/22
Maximum ratings
L6382D
3
3.1
Maximum ratings
Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol VCC VHVSU VBOOT VOUT ITPR(RMS) ITPR(PK) VTPR Pin 10 15 11 13 7 7 7 19 1, 2, 3, 4 Parameter IC supply voltage (ICC = 20mA) High voltage start-up generator voltage range Floating supply voltage Floating ground voltage Maximum TPR RMS current Maximum TPR peak current Maximum TPR voltage(1) CSI input voltage Logic input voltage Value Self-limited -0.3 to 600 -1 to VHVSU+VCC -1 to 600 200 600 14 -0.3 to 7 -0.3 to 7 15 to 400 15 to 600 -40 to +150 -40 to +125 V V V mA mA V V V KHz KHz C C Unit
9, 12, Operating frequency 17 5 Tstg TJ Operating frequency Storage temperature Ambient temperature operating range
1. Excluding operating mode
3.2
Thermal data
Table 3. Thermal data
Symbol RthJA Parameter Maximum thermal resistance junction-ambient Value 120 Unit C/W
6/22
L6382D
Electrical characteristics
4
Electrical characteristics
Table 4. Electrical characteristcs (TJ = 25C, VCC = 13V, CDRIVER = 1nF unless otherwise specified)
Symbol Pin Parameter Test condition Min Typ Max Unit
Supply voltage VCCON VCCOFF VCCSM VSMhys VREF(OFF) IvccON IvccSM 10 10 10 10 10 10 10 Turn-on voltage Turn-off voltage Save mode voltage Save mode hysteresys Reference turn-off Start-up current Save Mode current consumption (1) Quiescent current in operating mode Internal Zener LGI = HGI = high; no load on VREF. 16.5 17 13 7.5 12.75 0.12 5.7 14 8.25 13.8 0.16 6 15 9.2 14.85 0.2 6.4 150 190 150 230 2 18 V V V V V A A A mA V
Ivcc Vz
10 10
High voltage start-up IMSS ILSS 15 15 Maximum current VHVSU > 50V 20 40 mA A
Leakage current off VHVSU = 600V state
Two point regulator (TPR) protection TPRst 10 Vcc Protection level Vcc Turn-on level Operating mode Operating mode; after the first falling edge on LSG Operating mode; after the first falling edge on LSG ITPR = 200mA @ 600mA forward current. 14.0 14.5 15.0 V
TPR(ON)
10
12.5
13
13.5
V
TPR(OFF)
10
Vcc Turn-off level Output voltage on state Forward voltage drop Diode
12.45
12.95
13.48
V
7 7 7
2 2.3 5
V V A
Leakage current off VTPR = 13V state
7/22
Electrical characteristics Table 4. Electrical characteristcs (TJ = 25C, VCC = 13V, CDRIVER = 1nF unless otherwise specified) (continued)
Symbol Pin Parameter Test condition Min Typ
L6382D
Max
Unit
LSG, HEG & PFG drivers VOH(LS) 5, 9 17 5, 9 17 HIGH Output Voltage LOW Output Voltage Source Current Capability ILSG = IPFG = 10mA 12.5 IHEG = 2.5mA ILSG=IPFG=10mA 0.5 IHEG = 2.5mA LSG and PFG HEG LSG Sink Current Capability HEG PFG LSG TRISE Rise time HEG PFG LSG TFALL Fall time HEG PFG LSG; high to low and low to high TDELAY Propagation delay (input to output) HEG; high to low and low to high PFG; high to low PFG; low to high LSG RB Pull down Resistor HEG PFG HSG driver (voltages referred to OUT) VOH(HS) VOL(HS) 12 12 12 12 TRISE TFALL 12 12 HIGH Output Voltage LOW Output Voltage Sink Current Capability Source Current Capability Rise time Fall time Cload = 1nF Cload = 1nF IHSG = 10 mA IHSG = 10 mA 120 120 115 75 12.5 0.5 V V mA mA ns ns 20 50 10 120 50 120 70 250 115 300 60 75 110 40 300 200 250 200 ns ns ns ns ns ns ns ns ns ns K K K mA mA mA V V
VOL(LS)
8/22
L6382D
Electrical characteristics Table 4. Electrical characteristcs (TJ = 25C, VCC = 13V, CDRIVER = 1nF unless otherwise specified) (continued)
Symbol TDELAY RB Pin 12 12 Parameter Propagation delay (LGI to LSG) Pull down Resistor Test condition high to low and low to high to OUT 20 Min Typ Max 300 Unit ns K
High-side floating gate-driver supply ILKBOOT ILKOUT 11 13 VBOOT pin leakage current OUT pin leakage current Synchronous bootstrap diode onresistance Forward Voltage Drop Forward Current VREF VREF 20 20 20 20 Reference voltage Load regulation Voltage change VREF latched protection VREF Clamp @3mA VCC from 0 to VCCON during start-up;Vcc from VREF(OFF) to 0 during shut-down; Vref <2V -3 Save mode -3 15mA load. IRef = -3 to +30 mA 15mA load; Vcc = 9V to 15V 3.267 -20 3.3 3.366 2 15 2 V mV mV V VBOOT = 580V VOUT = 562V 5 5 A A
RDS(on)
VLVG = HIGH
150
W
at 10 mA forward current at 5V forward voltage drop 20
2.4
V mA
20
1.2
1.4
V
IREF
20
Current Drive Capability
+30 +10
mA mA
Overcurrent buffer stage VCSI ICSI 19 19 Comparator Level Input Bias Current Propagation delay 18 18 CSO turn off to LSG low VREF0.5V 0.5 V 0.537 0.56 0.582 500 200 V nA ns
High output voltage I CSO= 200A Low output voltage I CSO = -150A
9/22
Electrical characteristics Table 4. Electrical characteristcs (TJ = 25C, VCC = 13V, CDRIVER = 1nF unless otherwise specified) (continued)
Symbol DIM Normal Mode Time Out Vref enabling drivers TED Logic input 1 to 4 1 to 4 LGI Low Level Logic Input Voltage High Level Logic Input Voltage Pull down resistor 2.2 100 0.8 Time enabling drivers 70 100 3.0 10 130 Pin Parameter Test condition Min Typ
L6382D
Max
Unit
s V s
V V K
10/22
L6382D
Typical electrical performance
5
Typical electrical performance
Figure 4.
15 14 13 12
18
UVLO thresholds [V] vs. TJ
Figure 5.
VCC zener voltage [V] vs. TJ
21 20
Vcc(on)
19
11 10 9 8 7 -40 -25 0 25 50 75 100 125
17
Vcc(off)
16 15 14 -40 -25 0 25 50 75 100 125
Figure 6.
VREF [V] vs. TJ
Figure 7.
Overcurrent protection threshold [V] vs. TJ
3.5 3.45 3.4 3.35
600
580
560
3.3 3.25 3.2
540
520
3.15 3.1 -40 -25 0 25 50 75 100 125
500 -40
-25
0
25
50
75
100
125
Figure 8.
Propagation delays [ns] high to low vs. TJ
Figure 9.
Propagation delays [ns] low to high vs. TJ
300
300
250
250
200
200
150
HS LS
150
HS LS
100
100
PF
50
PF
50
0 -40 -25 0 25 50 75 100 125
0 -40 -25 0 25 50 75 100 125
11/22
Application information
L6382D
6
6.1
Application information
Power management
The L6382D has two stable states (SAVE MODE and OPERATING MODE) and two additional states that manage the Start-up and fault conditions (Figure 10): the Over Current Protection is a parallel asynchronous process enabled when in operating mode. Following paragraphs will describe each mode and the condition necessary to shift between them. Figure 10. State diagram
START-UP
VCCVCC>VCC(ON)
VCCSAVE MODE
VCCSHUT DOWN
VREF>3V & TED>10s
LGI low for more than 100s
VCC < VCC(OFF) or VREF<2V
OPERATING MODE
6.1.1
START-UP mode
With reference to the timing diagram of figure 11, when power is first applied to the converter, the voltage on the bulk capacitor builds up and the HV generator is enabled to operate drawing about 10mA. This current, diminished by the IC consumption (less than 150A), charges the bypass capacitor connected between pin Vcc and ground and makes its voltage rise almost linear. During this phase, all IC's functions are disabled except for:

the current sinking circuit on VREF pin that maintains low the voltage by keeping disabled the microcontroller connected to this pin; the High-Voltage Start-Up (HVSU) that is ON (conductive) to charge the external capacitor on pin Vcc.
As the Vcc voltage reaches the start-up threshold (14V typ.) the chip starts operating and the HV generator is switched off.
12/22
L6382D Summarizing: - - - - - the high-voltage start-up generator is active;
Application information
VREF is disabled with additional sinking circuit on pin VREF enabled; TPR is disabled; OCP is disabled; the drivers are disabled.
6.1.2
SAVE Mode
This mode is entered after the Vcc voltage reaches the turn-on threshold; the VREF is enabled in low current source mode to supply the C connected to it, whose wake-up required current must be less than 10mA: if no switching activity is detected at LGI input, the high voltage start-up generator cycles ON-OFF keeping the Vcc voltage between VccON and VccSM. Summarizing: - - - - - the high-voltage start-up generator is cycling; VREF is enabled in low source current capability (IREF 10mA); TPR circuit is disabled; OCP is disabled; the drivers are disabled.
If the Vcc voltage falls below the VREF(OFF) threshold, the device enters the start-up mode.
6.1.3
OPERATING Mode
After 10s in save mode and only if the voltage at VREF is higher than 3.0V, on the falling edge on the HGI input, the drivers are enabled as well as all the IC's functions; this is the mode correspondent to the proper lamp behavior. Summarizing: - - - - - HVSU is OFF VREF is enabled in high source current mode (IREF < 30mA) TPR circuit is enabled OCP is enabled the drivers are enabled
If there is no switching activity on LGI for more than 100s, the IC returns in save mode.
6.1.4
Shut down
This state permits to manage the fault conditions in operating mode and it is entered by the occurrence on one of the following conditions: 1. 2. Vcc13/22
Application information In this state the functions are: - - - - - The HVSU generator is ON VREF is enabled in low source current mode (IREF < 10mA) TPR is disabled OCP is disabled the drivers are disabled
L6382D
In this state if Vcc reaches VccOn, the device enters the save mode otherwise, if Vcc14/22
L6382D
Application information Figure 12. Timing sequences: save mode and operating mode
Vcc
VCCon VccSM VccOFF
TPR Switching
VREF
LGI
HGI
HVSU
10ms
OPERATING MODE
15/22
Block description
L6382D
7
7.1
Block description
Supply section
PUVLO (Power Under Voltage Lock Out): This block controls the power management of the L6382D ensuring the right current consumption in each operating state, the correct VREF current capability, the driver enabling and the high-voltage startup generator switching. During Start-up the device sinks the current necessary to charge the external capacitor on pin VCC from the high voltage bus; in this state the other IC's functions are disabled and the current consumption of the whole IC is less than 150A. When the voltage on VCC pin reaches VccON, the IC enters the save mode where the PUVLO block controls Vcc between VccON and VccSM by switching ON/OFF the high voltage start-up generator. HVSU (High-Voltage Start-Up generator): a 600V internal MOS transistor structure controls the Vcc supply voltage during start-up and save mode conditions and it reduces the power losses during operating Mode by switching OFF the MOS transistor. The transistor has a source current capability of up to 30mA. TPR (Two Point Regulator) & PWS: during normal mode, the TPR block controls the PSW switch in order to regulate the IC supply voltage (VCC) to a value in the range between TPR(ON) and TPR(OFF) by switching ON and OFF the PSW transistor Figure 11. - - - Vcc > TPRst: the PSW is switched ON immediately; TPR(ON) < Vcc < TPRst: the PSW is switched ON at the following falling edge of LGI; Vcc < TPR(OFF): the PSW is switched OFF at the following falling edge on LGI.
When the PSW switch is OFF, the diodes build a charge pump structure so that, connecting the TPR pin to a switching voltage (through a capacitor) it is possible to supply the low voltage section of the chip without adding any further external component. The diodes and the switch are designed to withstand a current of at least 200mARMS.
7.2
3.3V reference voltage
This block is used to supply the microcontroller; this source is able to supply 10mA in save mode and 30mA in operating mode; moreover, during start-up when VREF is not yet available, an additional circuit is ensures that, even sinking 3mA, the pin voltage doesn't exceed 1.2V. The reference is available until Vcc is above VREF(OFF); below that it turns off and the additional sinking circuit is enabled again.
16/22
L6382D
Block description
7.3
Drivers
LSD (Low Side Driver): it consists of a level shifter from 3.3V logic signal (LSI) to Vcc MOS driving level; conceived for the half-bridge low-side power MOS, it is able to source and sink 120mA (min). HSD (Level Shifter and High Side Driver): it consists of a level shifter from 3.3V logic signal (HGI) to the high side gate driver input up to 600V. Conceived for the half-bridge high-side power MOS, the HSG is able to source and sink 120mA. PFD (Power Factor Driver): it consists of a level shifter from 3.3V logic signal (PFI) to Vcc MOS driving level: the driver is able to source 120mA from Vcc to PFG (turn-on) and to sink 250mA to GND (turn-off); it is suitable to drive the MOS of the PFC preregulator stage. HED (Heat Driver): it consists of a level shifter from 3.3V logic signal (HEI) to Vcc MOS driving level; the driver is able to source 30mA from Vcc to HEG and to sink 75mA to GND and it is suitable for the filament heating when they are supplied by independent winding. Bootstrap Circuit: it generates the supply voltage for the high side Driver (HSD). A patented integrated bootstrap section replaces an external bootstrap diode. This section together with a bootstrap capacitor provides the bootstrap voltage to drive the high side power MOSFET. This function is achieved using a high voltage DMOS driver which is driven synchronously with the low side external power MOSFET. For a safe operation, current flow between BOOT pin and Vcc is always inhibited, even though ZVS operation may not be ensured.

7.4
Internal logic, over current protection (OCP) and interlocking function
The DIM (Digital Input Monitor) block manages the input signals delivered to the drivers ensuring that they are low during the described start-up procedure; the DIM block controls the L6382D behaviour during both save and operating modes. When the voltage on pin CSI overcomes the internal reference of 0.5V (typ.) the block latches the fault condition: in this state the OCP block forces low both HSG and LSG signals while CSO will be forced high. This condition remains latched until LSI and HSI are simultaneously low and CSI is below 0.5V. This function is suitable to implement an over current protection or hard-switching detection by using an external sense resistor. As the voltage on pin CSI can go negative, the current must be limited below 2mA by external components. Another feature of the DIM block is the internal interlocking that avoids cross-conduction in the half-bridge FET's: if by chance both HGI and LGI input's are brought high at the same time, then LSG and HSG are forced low as long as this critical condition persists.
17/22
Package mechanical data
L6382D
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
18/22
L6382D Table 5. SO-20 Mechanical data
mm. Dim. Min A A1 B C
D (1)
Package mechanical data
inch Max 2.65 0.30 0.51 0.32 13.00 7.60 Min 0.093 0.004 0.013 0.009 0.496 0.291 0.050 10.65 0.75 1.27 0.394 0.010 0.016 0.419 0.030 0.050 Typ Max 0.104 0.012 0.200 0.013 0.512 0.299
Typ
2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.0 0.25 0.40
E e H h L k ddd
0 (min.), 8 (max.) 0.10 0.004
Figure 13. Package dimensions
19/22
Order codes
L6382D
9
Order codes
Table 6. Order codes
Part number L6382D L6382DTR Package SO-20 SO-20 Packaging Tube Tape & Reel
20/22
L6382D
Revision history
10
Revision history
Table 7. Revision history
Date 15-Nov-2004 03-Jan-2005 23-Oct-2005 19-Apr-2006 22-May-2006 21-Mar-2007 Revision 1 2 3 4 5 6 First Issue Changed from "Preliminary Data" to "Final Datasheet" Many modified New template Typo error in block diagram, updated values in electrical charcteristics Table 4. Typo on Table 2 Changes
21/22
L6382D
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